Our mission is to formalize design & verification flow and provide relevant tools of mixed-signal system-on-chips (MS-SoCs). Today, the main challenge in validating MS SoCs is that the analog and digital subsystems are usually strongly coupled and thus they must be validated as a system, but the validation approaches for analog and digital blocks are completely different. We address this problem by creating high-level functional models of analog components in SystemVerilog, which is compatible with top-level digital system validation, and then provide a method of formal checking to ensure that these functional models match the operation of the transistor level implementations of these blocks.
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dave-eda-consulting.com

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