VHDL

During Synopsys synthesis, ordinary combinational logic will go through several of what are known as mapping optimizations. In a normal optimization, the synthesis tool will optimize in relation to the set constrains. It is usual to talk about moving along a "banana curve" on the area and time axes. This means that the tougher the timing constrains, the larger the design will be, and vice versa. The results from two different synthesis constrains applied on the same design are shown below.

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