BLACKFOREST EDA

ASIC / FPGA / SoC designs become increasingly complex with an ever increasing number of gates on chip. At the same time turnaround times shrink from one device generation to the next. We provide pre-defined and prooven design blocks to integrate into your modular design. Next step is to verify certain functionality with a reference test environment to conclude correct operation and earlier release to production. Both design blocks and verification references can be supported with specific verification tools and sourcing of local and remote experts to help with integration work and application specifc know-how... Our portfolio of Design IP, Verification IP and D&V - Productivity increases continuously. If you have specific requierements, we are happy to pre-qualify potential sources for you... HDL design productivity enhancements by help of production proven silicon Design IP, Verification IP including testsuites and behavioral models (BFM), tools for X-Verification and property..

Primary location: Meerbusch Germany