SANDPIPER

I'd like to see more people experimenting/playing with small CPU designs, extending our knowledge of what is possible with ‘minimal' amounts of hardware and software. Toward that end, I propose to lead an exploration of two CPUs, my QS5 Baby-RISC and a 16-bit implementation of Chuck Moore's dual-stack architecture. Both of these CPUs can be implemented in a small, low-cost, FPGA connected to a PC's parallel port. Of course, the software running on them will be Forth. We can meet monthly during the SVFIG morning session for as long as you are interested, with lots of work and electronic communication in between... The tools for the chip's software are in Forth, and will run under either Win32Forth or SwiftForth. The QS5 has a target assembler, dissasembler, metacompiler, and a few tools, plus the Forth source of e4th. I'm not sure what tools Dr. Ting has for the P16, but in the best Forth tradition, we'll develop what we need as we go... Prentice-Hall has published a Xilinx FPGA lab..