VERILOG.COM

Also of interests are a number of other verilog related resources which are available here; including an free editing mode for the verilog lanugage; links to various books that we have found useful in understanding verilog, and verification in general; links to tools that we have developed, use (and quite frankly that in our day job we sell)... Verilog HDL is a hardware description language used to design and document electronic systems. Verilog HDL allows designers to design at various levels of abstraction. It is the most widely used HDL with a user community of more than 50,000 active designers... Verilog HDL originated at Automated Integrated Design Systems (later renamed as Gateway Design Automation) in 1985. The company was privately held at that time by Dr. Prabhu Goel, the inventor of the PODEM test generation algorithm. Verilog HDL was designed by Phil Moorby, who was later to become the Chief Designer for Verilog-XL and the first Corporate Fellow at Cadence Design Systems...

Also known as: verilog