CALLIGOTECH

Already an established player in parallelizing and optimizing of large HPC Software applications, CalligoTech is now working on improving Hardware of computing at grass-root levels. Towards this, the Company has developed co-processor capable of doing computations using a new number system - the Posit Number System (PNS) - invented in 2017. Calligo has integrated the Coprocessor with a RISC-V Processor creating a highly power-efficient, and computationally more accurate CPU core. We call it as CRISP-core (Calligo RISC-v with Posit). Complementing this hardware, CalligoTech has modified RISC-V C/C+/gFortran compilers to generate Posit-enabled executables, without need for any source-level changes. Linux OS booting, compilation and running of C/C++ applications with posit-enabled executables was demonstrated at many international events; RISC-V Event at Switzerland (June 2019), HiPC Conference at Hyderabad (Dec 2019), at VLSID Conference at Bangalore (Jan 2020) and recently at HiPC..

Also known as: Calligo